In this paper a slew rate enhancement method using some extra paths in recycling folded cascode (RFC) amplifier is presented. The added transistors are in cut-off region in the small-signal operation and will be automatically turned on during slewing phase. Therefore, negative and positive slew rates are improved without increasing power dissipation in the small-signal operation. Simulation results in 90 nm CMOS technology show a 2.4 times enhancement in the average slew rate and a 69 % reduction in the settling time without affecting the gain bandwidth and power dissipation compared to the conventional RFC structure.
