In this paper, a useful frequency compensation technique for a three-stage fully differential amplifier with a recycling folded cascode (RFC) input stage structure is presented. The proposed compensation technique is based on using flipped voltage follower (FVF) cell in the RFC structure. This approach merges improved cascode and indirect compensation techniques that the output node of the FVF cell is used for the second one. The proposed circuit yields a higher gain bandwidth (GBW) than the other indirect compensation techniques at the cost of a more complex design procedure. This idea is simulated using 0.18 µm CMOS technology. Simulation results show a 125 dB DC gain, a 41 V/µs slew rate, a 44 MHz GBW, and a phase margin of 76°. The amplifier consumes 695 µW while driving a 30-pF load.
