In the current distributed integrated circuits (IC) industry, the possibility of adversarial hardware attacks cannot be ignored. Hardware Trojans (HT) attacks may lead to information leakage or failure in security-critical systems. The wide range of HT types and related insertion strategies makes the HT detection process very complex. Consequently, developing the IC design methodologies that are robust against HT insertion would be of great merit. To measure the HT robustness, a vulnerability analysis of the proposed circuits should be performed which involves several interrelated factors (e.g. the layout of white spaces distribution, the unutilized routing resources, activity of the circuit nodes, the delay values of circuit paths, etc.). In this paper, a novel framework is proposed to classify the IC vulnerability level. First, a comprehensive dataset is generated considering different HTs insertion into the ISCAS 85 and ISCAS 89 benchmark circuits. Then extraction of efficient features from the input image is accomplished by pre-trained deep neural networks. Finally, the vulnerability level (which is defined as low vulnerable, moderately vulnerable, and highly vulnerable) of every circuit is extracted using various trained classifiers (Ensemble, SVM, Naïve Bayes, and KNN). Simulation results confirm a 25% improvement in classification accuracy in the most successful classifier (97%) compared with the most successful previous study (72%).
