2026/8/4
Hadi Jahanirad

Hadi Jahanirad

Academic rank: Associate Professor
ORCID:
Education: PhD.
ResearchGate:
Faculty: Faculty of Engineering
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E-mail: h.jahanirad [at] uok.ac.ir
ScopusId: Link
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Research

Title
A Transistor-Level Reliability Estimation of CNTFET-Based Multivalued Logic Circuits
Type
JournalPaper
Keywords
Carbon nanotube field effect transistor (CNTFET), error probability calculation, multivalued logic (MVL), reliability analysis, stuck at faults, ternary logic.
Year
2026
Journal IEEE Transactions on Reliability
DOI
Researchers Hadi Jahanirad

Abstract

Multivalued logic (MVL) circuits use more than two voltage levels for data representation. MVL systems outperform binary counterparts regarding power consumption, speed, and chip area. Due to the best tradeoff between power and delay, the carbon nanotube field effect transistor (CNTFET) becomes the widely used device to implement MVL circuits. One critical problem regarding such circuits is the high fault occurrence probability of CNTFETs. The occurrence of these faults results in the transition of the correct value in the gate output to another incorrect logic value that affects the circuit’s functionality. In this article, we develop an accurate and fast reliability evaluation methodology for CNTFET-based MVL circuits wherein the fault occurrence probabilities of the gate’s CNTFETs are combined with the error probabilities of the logic gate’s inputs to calculate the transition probability of the gate’s output among various logic levels. Having the transition probabilities for all circuit’s nodes, the reliability of the correct operation of the MVL circuit would be assessed. Simulation results for various MVL-based circuits showed that the proposed method estimates reliability with more than 97.5% accuracy and almost 0.5 × 106 times faster than the Monte Carlo-based estimation. Moreover, the proposed methodology could be utilized to extract the range of the MVL-based gate reliability for various input vectors, which could be utilized to improve the robustness level of them in the circuit design process.