— Nowadays, the application of chaotic systems in digital image encryption received considerable attention. Since these systems have non-linear and complex structures, implementing chaotic systems on FPGA is encountered with design considerations. Designing these systems with hardware description languages such as Verilog and VHDL can lead to high cost and latency design. This paper presents a low-cost and high-performance approach for implementing chaotic systems on FPGA using high-level synthesis tools. First, we discretize the chaotic system with Forward Euler and Runge-Kutta’s fourthorder algorithm. Second, C++ codes with hardware aspects are written for these discretized models in the HLS compiler. Finally, we accelerate the design with exclusive directives in HLS and synthesize the design on target FPGA. In this design, we use a 32-bit fixed-point IQ-Math standard number (16I-16Q) for data, and the target device is Xilinx Virtex-7 XC7VX330T. Proposed modules are implemented and synthesized utilizing Vivado HLS. The proposed implementation method reduces the latency, the number of Flip-Flops, and the number of Lookup tables with the ratio of 5.7, 13.48, and 8.14 on average, respectively in comparison with previous studies.
