In nanometric integrated circuits, reliability has become one of the main design measures. This makes the reliability evaluation process an inevitable part in the circuit design flow. In this paper, a probabilistic method has been developed for reliability evaluation of combinational logic circuits. At the core of the proposed method, correct and incorrect probabilities for binary logic values (0 and 1) of a circuit’s gate are derived using probability transfer matrix and the correct and incorrect probabilities of gate’s inputs. An efficient approach has been proposed to handle the reconvergent fanouts problem using correlation coefficients concept. Both accuracy and scalability of the proposed method have been illustrated by various simulations on ISCAS 85 and LGSynth91 benchmark circuits. The results have shown a less than 2% average error for reliability estimation comparing Monte Carlo simulation. Comparing to state-of-the-art methods the proposed approach has a better performance in reliability estimation and algorithm runtime.
