In concurrent online BIST, testing is conducted simultaneously during normal functional operation. A fault model enables a structural test to be undertaken for a long time while simultaneously identifying critical faults. As a result of continuous testing, intermittent and transient faults are more likely to be detected. The number of required cycles for completion of a concurrent test, known as concurrent test latency (CTL), is a critical parameter for a concurrent BIST design. Most of the existing methods have impractical CTL, while others suffer from a high hardware overhead or a presence of a substantial combinational circuit. These methods are also incompatible with situations where parameters need to be adjusted, like when the hardware is more critical than CTL and vice versa. This paper proposes an efficient concurrent BIST to overcome the mentioned challenges. The main components of the proposed design consist of LFSRs and a small decoding combinational module result in low hardware overhead. In addition, CTL and hardware overhead can be adjusted and tuned in an acceptable range using the proposed method. Compared to the most efficient method, the proposed method achieves a 10% reduction in hardware overhead for large-scale circuits by keeping the CTL minimum. The different experiments demonstrate the capability of tuning between CTL and hardware overhead for the proposed BIST design. In the case that CTL and hardware overhead are equally important, the proposed method significantly lowers CTL compared to previous methods, while hardware overhead is only about 4% higher than the previous method for both large-scale (LS) and very large scale (VLS) circuits.
