Three Dimensional Field Programmable Gate Arrays (3D FPGAs) recently are presented as the next generation of the FPGA family to continue the integration of more transistors on a single chip seamlessly. The 3D FPGA are fabricated by stacking several layers of semiconductor substrates and the interconnection among layers are realized using Through Silicon Vias (TSVs). Despite their benefits regarding less area and higher speed, 3D FPGAs encounter two major problems; huge size of single TSV and trapping generated heat in inner layers. To handle these problems, we propose a complete Computer Aided Design (CAD) flow to implement an arbitrary logic circuit on 3D FPGA. Partitioning, Placement, and Routing are primary stages of the proposed CAD flow. The partitioning and placement stages of the flow are based on Simulated Annealing algorithm. Furthermore, the routing stage is a modified version of the Pathfinder algorithm. Unbalanced SA based partitioning tremendously reduces the required TSVs along with distribution of highly active circuit’s modules on the bottom layers and constructing thermal channels facilitate transferring the generated heat in intermediate layers. Simulation results show more than 60%, 65%, and 23% reduction in TSV count, heat transfer performance, and area respectively, along with 4% increase in critical path delay. In addition, comparison between 2D FPGA and 3D FPGA with our proposed architecture (including 2 tier), shows that the circuit speed increases by 28.61%, and minimum channel width decreases by 30.47%. Finally, the results of comparison between 2-tier and 4-tier in 3D FPGA show that circuit speed and minimum channel width increase by 15.95% and 15.92% in 4-tier, respectively.
